Add styling on links
This commit is contained in:
143
static/assets/gowin-n305/mstconfig-query-cx5.txt
Normal file
143
static/assets/gowin-n305/mstconfig-query-cx5.txt
Normal file
@ -0,0 +1,143 @@
|
||||
|
||||
Device #1:
|
||||
----------
|
||||
|
||||
Device type: ConnectX5
|
||||
Name: MCX542B-ACAN_C07_Ax
|
||||
Description: ConnectX-5 EN network interface card for OCP; with host management; 25GbE dual-port SFP28; PCIe3.0 x8; no bracket Halogen free
|
||||
Device: 0e:00.0
|
||||
|
||||
Configurations: Next Boot
|
||||
MEMIC_BAR_SIZE 0
|
||||
MEMIC_SIZE_LIMIT _256KB(1)
|
||||
HOST_CHAINING_MODE DISABLED(0)
|
||||
HOST_CHAINING_DESCRIPTORS Array[0..7]
|
||||
HOST_CHAINING_TOTAL_BUFFER_SIZE Array[0..7]
|
||||
FLEX_PARSER_PROFILE_ENABLE 0
|
||||
FLEX_IPV4_OVER_VXLAN_PORT 0
|
||||
ROCE_NEXT_PROTOCOL 254
|
||||
ESWITCH_HAIRPIN_DESCRIPTORS Array[0..7]
|
||||
ESWITCH_HAIRPIN_TOT_BUFFER_SIZE Array[0..7]
|
||||
PF_BAR2_SIZE 0
|
||||
NON_PREFETCHABLE_PF_BAR False(0)
|
||||
VF_NODNIC_ENABLE False(0)
|
||||
NUM_PF_MSIX_VALID True(1)
|
||||
NUM_OF_VFS 8
|
||||
NUM_OF_PF 2
|
||||
PF_BAR2_ENABLE False(0)
|
||||
SRIOV_EN True(1)
|
||||
PF_LOG_BAR_SIZE 5
|
||||
VF_LOG_BAR_SIZE 0
|
||||
NUM_PF_MSIX 63
|
||||
NUM_VF_MSIX 11
|
||||
INT_LOG_MAX_PAYLOAD_SIZE AUTOMATIC(0)
|
||||
PARTIAL_RESET_EN False(0)
|
||||
SW_RECOVERY_ON_ERRORS False(0)
|
||||
RESET_WITH_HOST_ON_ERRORS False(0)
|
||||
DISABLE_SLOT_POWER_LIMITER True(1)
|
||||
ADVANCED_POWER_SETTINGS True(1)
|
||||
CQE_COMPRESSION BALANCED(0)
|
||||
IP_OVER_VXLAN_EN False(0)
|
||||
MKEY_BY_NAME False(0)
|
||||
ESWITCH_IPV4_TTL_MODIFY_ENABLE False(0)
|
||||
PRIO_TAG_REQUIRED_EN False(0)
|
||||
UCTX_EN True(1)
|
||||
PCI_ATOMIC_MODE PCI_ATOMIC_DISABLED_EXT_ATOMIC_ENABLED(0)
|
||||
LRO_LOG_TIMEOUT0 6
|
||||
LRO_LOG_TIMEOUT1 7
|
||||
LRO_LOG_TIMEOUT2 8
|
||||
LRO_LOG_TIMEOUT3 13
|
||||
LOG_DCR_HASH_TABLE_SIZE 11
|
||||
DCR_LIFO_SIZE 16384
|
||||
ROCE_CC_PRIO_MASK_P1 255
|
||||
ROCE_CC_PRIO_MASK_P2 255
|
||||
CLAMP_TGT_RATE_AFTER_TIME_INC_P1 True(1)
|
||||
CLAMP_TGT_RATE_P1 False(0)
|
||||
RPG_TIME_RESET_P1 300
|
||||
RPG_BYTE_RESET_P1 32767
|
||||
RPG_THRESHOLD_P1 1
|
||||
RPG_MAX_RATE_P1 0
|
||||
RPG_AI_RATE_P1 5
|
||||
RPG_HAI_RATE_P1 50
|
||||
RPG_GD_P1 11
|
||||
RPG_MIN_DEC_FAC_P1 50
|
||||
RPG_MIN_RATE_P1 1
|
||||
RATE_TO_SET_ON_FIRST_CNP_P1 0
|
||||
DCE_TCP_G_P1 1019
|
||||
DCE_TCP_RTT_P1 1
|
||||
RATE_REDUCE_MONITOR_PERIOD_P1 4
|
||||
INITIAL_ALPHA_VALUE_P1 1023
|
||||
MIN_TIME_BETWEEN_CNPS_P1 0
|
||||
CNP_802P_PRIO_P1 6
|
||||
CNP_DSCP_P1 48
|
||||
CLAMP_TGT_RATE_AFTER_TIME_INC_P2 True(1)
|
||||
CLAMP_TGT_RATE_P2 False(0)
|
||||
RPG_TIME_RESET_P2 300
|
||||
RPG_BYTE_RESET_P2 32767
|
||||
RPG_THRESHOLD_P2 1
|
||||
RPG_MAX_RATE_P2 0
|
||||
RPG_AI_RATE_P2 5
|
||||
RPG_HAI_RATE_P2 50
|
||||
RPG_GD_P2 11
|
||||
RPG_MIN_DEC_FAC_P2 50
|
||||
RPG_MIN_RATE_P2 1
|
||||
RATE_TO_SET_ON_FIRST_CNP_P2 0
|
||||
DCE_TCP_G_P2 1019
|
||||
DCE_TCP_RTT_P2 1
|
||||
RATE_REDUCE_MONITOR_PERIOD_P2 4
|
||||
INITIAL_ALPHA_VALUE_P2 1023
|
||||
MIN_TIME_BETWEEN_CNPS_P2 0
|
||||
CNP_802P_PRIO_P2 6
|
||||
CNP_DSCP_P2 48
|
||||
LLDP_NB_DCBX_P1 False(0)
|
||||
LLDP_NB_RX_MODE_P1 OFF(0)
|
||||
LLDP_NB_TX_MODE_P1 OFF(0)
|
||||
LLDP_NB_DCBX_P2 False(0)
|
||||
LLDP_NB_RX_MODE_P2 OFF(0)
|
||||
LLDP_NB_TX_MODE_P2 OFF(0)
|
||||
DCBX_IEEE_P1 True(1)
|
||||
DCBX_CEE_P1 True(1)
|
||||
DCBX_WILLING_P1 True(1)
|
||||
DCBX_IEEE_P2 True(1)
|
||||
DCBX_CEE_P2 True(1)
|
||||
DCBX_WILLING_P2 True(1)
|
||||
KEEP_ETH_LINK_UP_P1 True(1)
|
||||
KEEP_IB_LINK_UP_P1 False(0)
|
||||
KEEP_LINK_UP_ON_BOOT_P1 False(0)
|
||||
KEEP_LINK_UP_ON_STANDBY_P1 False(0)
|
||||
KEEP_ETH_LINK_UP_P2 True(1)
|
||||
KEEP_IB_LINK_UP_P2 False(0)
|
||||
KEEP_LINK_UP_ON_BOOT_P2 False(0)
|
||||
KEEP_LINK_UP_ON_STANDBY_P2 False(0)
|
||||
NUM_OF_VL_P1 _4_VLs(3)
|
||||
NUM_OF_TC_P1 _8_TCs(0)
|
||||
NUM_OF_PFC_P1 8
|
||||
NUM_OF_VL_P2 _4_VLs(3)
|
||||
NUM_OF_TC_P2 _8_TCs(0)
|
||||
NUM_OF_PFC_P2 8
|
||||
DUP_MAC_ACTION_P1 LAST_CFG(0)
|
||||
SRIOV_IB_ROUTING_MODE_P1 LID(1)
|
||||
IB_ROUTING_MODE_P1 LID(1)
|
||||
DUP_MAC_ACTION_P2 LAST_CFG(0)
|
||||
SRIOV_IB_ROUTING_MODE_P2 LID(1)
|
||||
IB_ROUTING_MODE_P2 LID(1)
|
||||
PCI_WR_ORDERING per_mkey(0)
|
||||
MULTI_PORT_VHCA_EN False(0)
|
||||
PORT_OWNER True(1)
|
||||
ALLOW_RD_COUNTERS True(1)
|
||||
RENEG_ON_CHANGE True(1)
|
||||
TRACER_ENABLE True(1)
|
||||
IP_VER IPv4(0)
|
||||
BOOT_UNDI_NETWORK_WAIT 0
|
||||
UEFI_HII_EN False(0)
|
||||
BOOT_DBG_LOG False(0)
|
||||
UEFI_LOGS DISABLED(0)
|
||||
BOOT_VLAN 1
|
||||
LEGACY_BOOT_PROTOCOL PXE(1)
|
||||
BOOT_LACP_DIS True(1)
|
||||
BOOT_VLAN_EN False(0)
|
||||
BOOT_PKEY 0
|
||||
DYNAMIC_VF_MSIX_TABLE False(0)
|
||||
ADVANCED_PCI_SETTINGS False(0)
|
||||
SAFE_MODE_THRESHOLD 10
|
||||
SAFE_MODE_ENABLE True(1)
|
||||
Reference in New Issue
Block a user